Report Number: CSL-TR-94-605
Institution: Stanford University, Computer Systems Laboratory
Title: Performance and Area Analysis of Processor Configurations
with Scaling of Technology
Author: Fu, Steve
Author: Flynn, Michael J.
Date: March 1994
Abstract: The increasing density of transistors on integrated circuits
and the increasing sensitivity toward costs have stimulated
interest in developing techniques for relating transistor
count to performance. This paper maps different processor
configuration to transistor level area models and proposes an
optimum evolution path of processor design as minimum feature
size of technology is scaled. A parameter for measuring
incremental performance improvement with respect to
increasing transistor count is proposed.