Report Number: CSL-TR-94-600
Institution: Stanford University, Computer Systems Laboratory
Title: Environmental Limits on the Performance of CMOS
Author: Nowka, Kevin J.
Author: Flynn, Michael J.
Date: January 1994
Abstract: Wave-pipelining is a circuit design technique which allows
digital synchronous systems to be clocked at rates higher
than can be achieved with conventional pipelining techniques.
Wave-pipelining has been successfully applied to the design
of SSI processor functional units, a Bipolar Population
Counter, a CMOS adder, CMOS multipliers, and several simple
CMOS circuits. For controlled operating environments,
speed-ups of 2 to 10 have been reported for these designs.
This report details the effects of temperature variation,
supply voltage variation, and process variation on
wave-pipelined static CMOS designs, derives limits for the
performance of wave-pipelined circuits due to these
variations, and compares the performance effects with those
of traditional pipelined circuits.
This study finds that wave-pipelined circuits designed for
commercial operating environments are limited to 2 to 3 waves
per pipeline stage when clocked from a fixed frequency
source. Variable rate, internal clocking can approach the
theoretical limit of waves at a cost of interface complexity.