Report Number: CSL-TR-91-459
Institution: Stanford University, Computer Systems Laboratory
Title: On fast IEEE rounding
Author: Quach, Nhon
Author: Takagi, Naofumi
Author: Flynn, Michael J.
Date: January 1991
Abstract: A systematic general rounding procedure is proposed. This
procedure consists of 2 steps: constructing a rounding table
and selecting a prediction scheme. Optimization guidelines
are given in each step to minimize the hardware used. This
procedure-based rounding method has the additional advantage
that verification and generalization are trivial. Two
rounding hardware models are described. The first is shown to
be identical to that reported by Santoro, et al. The second
is more powerful, providing solutions where the first fails.
Applying this approach to the IEEE rounding modes for
high-speed conventional binary multipliers reveals that round
to infinity is more difficult to implement than the round to
nearest mode; more adders are potentially needed. Round to
zero requires the least amount of hardware.
A generalization of this procedure to redundant binary
multipliers reveals two major advantages over conventional
binary multipliers. First, the computation of the sticky bit
consumes considerably less hardware. Second, implementing round
to positive and minus infinity modes does not require the
examination of the sticky bit, removing a possible worst-case
A generalization of this approach to addition produces a
similar solution to that reported by Quach and Flynn.
Although generalizable to other kinds of rounding as well as
other arithmetic operations, we only treat the case of IEEE
rounding for addition and multiplication; IEEE rounding
because it is the current standard on rounding, addition and
multiplication because they are the most frequently used
arithmetic operations in a typical scientific computation.