Report Number: CSL-TR-90-454
Institution: Stanford University, Computer Systems Laboratory
Title: Page allocation to reduce access time of physical caches
Author: Bray, Brian K.
Author: Lunch, William L.
Author: Flynn, Michael J.
Date: November 1990
Abstract: A simple modification to an operating system's page
allocation algorithm can give physically addressed caches the
speed of virtually addressed caches. Colored page allocation
reduces the number of bits that need to be translated before
cache access, allowing large low-associativity caches to be
indexed before address translation, which reduces the latency
to the processor. The colored allocation also has other
benefits: caches miss less (in general) and more uniformly,
and the inclusion principle holds for second level caches
with less associativity. However, the colored allocation
requires main memory partitioning, and more common bits for
shared virtual addresses. Simulation results show high
non-uniformity of cache miss rates for normal allocation.
Analysis demonstrates the extent of second-level cache
inclusion, and the reduction in effective main-memory due to