Report Number: CSL-TR-90-442
Institution: Stanford University, Computer Systems Laboratory
Title: An improved algorithm for high-speed floating-point addition
Author: Quach, Nhon T.
Author: Flynn, Michael J.
Date: August 1990
Abstract: This paper describes an improved, IEEE conforming
floating-point addition algorithm. This algorithm has only
one addition step involving the significand in the
worst-case path, hence offering a considerable speed
advantage over the existing algorithms, which typically
require two to three addition steps.