Report Number: CSL-TR-89-398
Institution: Stanford University, Computer Systems Laboratory
Title: The relative effects of optimization on instruction architecture performance
Author: Cuderman, K. J.
Author: Flynn, M. J.
Date: October 1989
Abstract: The Stanford Architect's Workbench is a simulation platform
used to evaluate the impact of optimization on the relative
performance of instruction set architectures. The total
impact optimization makes on an application is the combined
interaction of the optimizer, the architecture, and the cache
configuration. The relative performance of seven
architectures are compared using a suite of six application
Optimization reduces the number of executed instructions, but
its effectiveness varies with architecture. Register
architectures capitalize on temporaries introduced by
optimization without incurring penalties for moving data.
Short instructions for register operations reduce the
instruction bandwidth in addition to reducing the number of
Reducing the number of executed instructions does not yield a
reduction in memory traffic. Optimization only slightly
alters the program working set size. An instruction cache
quickly masks the effect of optimization. The result is that
the instruction memory traffic remains almost constant for an