Report Number: CSL-TR-88-367
Institution: Stanford University, Computer Systems Laboratory
Title: An overview of VAL
Author: Augustin, Larry M.
Author: Gennart, Benoit A.
Author: Huh, Youm
Author: Luckham, David C.
Author: Stanculescu, Alec G.
Date: October 1988
Abstract: VAL (VHDL Annotation Language) provides a small number of new
language constructs to annotate VHDL hardware descriptions.
VAL annotations, added to the VHDL entity declaration in the
form of formal comments, express intended behavior common to
all architectural bodies of the entity. Annotations are
expressed as parallel processes that accept streams of input
signals and generate constraints on output streams. VAL views
signals as streams of values ordered by time. Generalized
timing expressions allow the designer to refer to relative
points on a stream. No concept of preemptive delayed
assignment or inertial delay are needed when referring to
different relative points in time on a stream. The VAL
abstract state model permits abstract data types to be used
in specifying history dependent device behavior. Annotations
placed inside a VHDL architecture define detailed
correspondences between the behavior specification and
architecture. The result is a simple but expressive language
extension of VHDL with possible applications to automatic
checking of VHDL simulations, hierarchical design, and
automatic verification of hardware designs in VHDL.