Report Number: CSL-TR-87-339
Institution: Stanford University, Computer Systems Laboratory
Title: MIPS-X: the external interface
Author: Salz, Arturo
Author: Agarwal, Anant
Author: Chow, Paul
Date: November 1987
Abstract: MIPS-X is a 20-MIPS-peak VLSI processor designed at Stanford University. This document describes the external interface of MIPS-X and the organization of the MIPS-X processor system, including the external cache and coprocessors. The external interface has been designed to optimize the paths between the processor, the external cache and the coprocessors. The signals used by the processor and their timing are documented here. Signal use and timings during exceptions and cache misses are also shown.