Report Number: CSL-TR-86-303
Institution: Stanford University, Computer Systems Laboratory
Title: The semantics of timing constructs in hardware description languages
Author: Luckham, David C.
Author: Huh, Youm
Author: Stanculescu, Alec G.
Date: August 1986
Abstract: Three different approaches to the representation of time in high level hardware design languages are described and compared. The first is the timed assignment statement of ADLIB/SABLE which anticipates future events. The second is the timed assignment of VHDL which predicts future events and allows predictions to be preempted by other predictions. The third is a new proposed method of expressing time dependency by qualifying expressions so that their values are required to be constant over a specified time interval. Examples comparing these three approaches are given. It is shown how time-qualified expressions could be introduced into a hardware description language. The possibility of proving correctness of hardware models in this language is illustrated.
http://i.stanford.edu/pub/cstr/reports/csl/tr/86/303/CSL-TR-86-303.pdf