Report Number: CSL-TR-84-259
Institution: Stanford University, Computer Systems Laboratory
Title: Organization and VLSI implementation of MIPS
Author: Przybylski, Steven A.
Author: Gross, Thomas R.
Author: Hennessy, John L.
Author: Jouppi, Norman P.
Author: Rowen, Christopher
Date: April 1984
Abstract: MIPS is an 32-bit, high performance processor architecture
implemented as an nMOS VLSI chip. The processor uses a low
level, streamlined instruction set coupled with a fast
pipeline to achieve an instruction rate of two million
instructions per second. Close interaction between the
processor design and compilers for the machine yields
efficient execution of programs on the chip. Simplifying the
instruction set and the requirements placed on the hardware
by the architecture, facilitates both processor control and
interrupt handling in the pipeline. High speed MOS circuit
design techniques and a sophisticated timing methodology
enable the processor to achieve a 250nS clock cycle.