Report Number: CSL-TR-83-242
Institution: Stanford University, Computer Systems Laboratory
Title: Fault simulation using ADLIB-SABLE
Author: Ghosh, Sumit
Author: vanCleemput, Willem
Date: March 1983
Abstract: This technical report presents work in the area of deductive
fault simulation. This technique, one of the three fault
simulation techniques discussed in the literature, has been
implemented in ADLIB-SABLE, a hierarchical multi-level
simulator designed and used at Stanford University. Most of
the fault models illustrated in this report consider only two
fault types: single stuck-at-0 and single stuck-at-Z (high
impedance). Gate level fault models have been built for most
commonly used gates. The ability to model the fault behavior
of functional blocks in ADLIB-SABLE is also demonstrated. The
motivation is that for many functional blocks, a gate level
description may not be available or that the designer wishes
to sacrifice detailed analysis for a higher simulation speed.
Functional fault models are built for many commonly used
blocks, using a decomposition technique. The ratio of
functional fault simulation speed to gate level fault
simulation speed has been observed to be of the order of 5
for the typical functional block sizes considered. The ratio
however, is not the upper limit and will be larger for
larger-sized functional blocks. It was also proved that the
functional fault models are invariant with respect to the
internal implementation details. A design discipline for
sequential circuits is worked out which allows deductive
fault simulation. Extensions to the simple (0,1) deductive
techniques are studied and the fault models built in the
extended domain are observed to be useful in modelling gates
of some technologies. A comparison between deductive and
concurrent fault simulation methods is given. Performance of
deductive fault simulation, implemented in ADLIB-SABLE, shows
that for sequential as well as combinational circuits, the
CPU time increases linearly with increasing number of
components simulated, an advantage over fault simulators
which simulate one fault at a time and display a quadratic
behavior.
http://i.stanford.edu/pub/cstr/reports/csl/tr/83/242/CSL-TR-83-242.pdf