Report Number: CSL-TR-83-236
Institution: Stanford University, Computer Systems Laboratory
Title: Design of a high performance VLSI processor
Author: Hennessy, John L.
Author: Jouppi, Norman
Author: Przybylski, Steven
Author: Rowen, Christopher
Author: Gross, Thomas
Date: February 1983
Abstract: Current VLSI fabrication technology makes it possible to design a 32-bit CPU on a single chip. However, to achieve high performance from that processor, the architecture and implementation must be carefully designed and tuned. The MIPS processor incorporates some new architectural ideas into a single-chip, nMOS implementation. Processor performance is obtained by the careful integration of the software (e.g., compilers), the architecture, and the hardware implementation. This integrated view also simplifies the design, making it practical to implement the processor at a university.