Report Number: CSL-TR-81-223
Institution: Stanford University, Computer Systems Laboratory
Title: MIPS: a VLSI processor architecture
Author: Hennessy, John L.
Author: Jouppi, Norman
Author: Baskett, Forest
Author: Gill, John
Date: November 1981
Abstract: MIPS is a new single chip VLSI processor architecture. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.