Report Number: CSL-TR-77-142
Institution: Stanford University, Computer Systems Laboratory
Title: Optimal layout of CMOS functional arrays
Author: Uehara, T.
Author: vanCleemput, Willem M.
Date: March 1978
Abstract: Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.