Report Number: CS-TR-89-1266
Institution: Stanford University, Department of Computer Science
Title: Multi-level shared caching techniques for scalability in
Author: Cheriton, David R.
Author: Goosen, Hendrik A.
Author: Boyle, Patrick D.
Date: May 1989
Abstract: The problem of building a scalable shared memory
multiprocessor can be reduced to that of building a scalable
memory hierarchy, assuming interprocessor communication is
handled by the memory system. In this paper, we describe the
VMP-MC design, a distributed parallel multi-computer based on
the VMP multiprocessor design, that is intended to provide a
set of building blocks for configuring machines from one to
several thousand processors. VMP-MC uses a memory hierarchy
based on shared caches, ranging from on-chip caches to
board-level caches connected by busses to, at the bottom, a
high-speed fiber optic ring. In addition to describing the
building block components of this architecture, we identify
the key performance issues associated with the design and
provide performance evaluation of these issues using
trace-drive simulation and measurements from the VMP.