Report Number: CS-TR-86-1105
Institution: Stanford University, Department of Computer Science
Title: Software-controlled caches in the VMP multiprocessor
Author: Cheriton, David R.
Author: Slavenburg, Gert A.
Author: Boyle, Patrick D.
Date: March 1986
Abstract: VMP is an experimental multiprocessor that follows the
familiar basic design of multiple processors, each with a
cache, connected by a shared bus to global memory. Each
processor has a synchronous, virtually addressed, single
master connection to its cache, providing very high memory
bandwidth. An unusually large cache page size and fast
sequential memory copy hardware make it feasible for cache
misses to be handled in software, analogously to the handling
of virtual memory page faults. Hardware support for cache
consistency is limited to a simple state machine that
monitors the bus and interrupts the processor when a cache
consistency action is required.
In this paper, we show how the VMP design provides the high
memory bandwidth required by modern high-performance
processors with a minimum of hardware complexity and cost. We
also describe simple solutions to the consistency problems
associated with virtually addressed caches. Simulation
results indicate that the design achieves good performance
providing data contention is not excessive.